First Look At DDR3

Initial benchmarks of the next-generation DDR memory

Having been observing the desktop memory market for years, we can see that the highest-priority line of DDR SDRAM development has been its bandwidth growth (which depends directly on its clock rate) and latency reduction. At that, power consumption reduction is the second most important matter, and memory capacity is the third. To all appearances, the first trend is considered more important. Therefore engineers advance it constantly (within the same evolutional step of a given technology - for example, a gradual upgrade from DDR2-400 to DDR2-800 and higher). Implementation of the other tasks usually requires a certain evolutional leap in technologies (for example, the upgrade from DDR to DDR2). Indeed, increasing memory bus frequency has a negative effect on its power consumption, so other approaches are necessary to solve the power saving problem. Moreover, the situation is usually complicated by the fact that solution of this problem contradicts the general line of memory development. It consists in reaching higher bandwidth (frequencies) and lower latencies. Indeed, it's well known that the first modifications of DDR2 memory were noticeably outperformed by DDR memory of the same frequency. Nevertheless, unlimited frequency growth (and latency reduction) is impossible within a single memory technology - it's limited by certain physical reasons (heat release in the first place). So evolutional advances in memory technology are necessary, they are stipulated not only by caring for lesser power consumption.

That was the case with the first evolutional advance in DDR SDRAM technologies - the upgrade from DDR to DDR2. The first samples of DDR operated just at 100 MHz (DDR-200), then the frequency gradually grew to 200 MHz (DDR-400). At the same time latencies were reduced - initial 3-3-3-8 timings changed to 2-2-2-5. Then there appeared higher-frequency DDR memory modules (up to 300 MHz, that is DDR-600), but they were not officially accepted by the JEDEC standard. Increasing memory frequency or reducing latencies required increasing memory voltage from 2.5V to about 2.85V. The problem of excessive heat release was usually solved by using usual heatspreaders.

When further increase in DDR memory frequency was practically impossible, there appeared the second generation of DDR SDRAM desktop memory - DDR2. It gradually proved it competitiveness and replaced the old generation of DDR memory. Initial modifications of DDR2 memory were represented by 200 MHz (DDR2-400) and 266 MHz (DDR2-533) models - DDR2 started to evolve from the point where DDR (officially) ended its existence. Moreover, the initial DDR2 standard provided for memory modules of much higher frequencies than usual DDR - 333 MHz DDR2-667 modules and 400 MHz DDR2-800 modules. DDR2 chips were based on the new process technology, which allowed to power memory from just 1.8V (one of the power saving factors) and to reach higher memory capacities.

How could DDR2 reach high frequencies (and consequently high memory bandwidth) and simultaneously reduce its power consumption versus DDR? Did DDR2 have only advantages over DDR, or were there drawbacks as well? We'll make a brief digression to theory to answer these questions. First of all, let's have a look at the simplified functional diagram of DDR memory (Picture 1).

Picture 1. Schematic diagram of data transfer in a DDR-400 chip.

Memory chips transfer data to a memory controller via the external data bus on the rising and falling edge of the clock. That's the essence of the Double Data Rate technology. That's why the rating or the effective frequency of DDR memory is always doubled (for example, DDR-400 at 200 MHz data bus). So, the efficient frequency of the DDR-400 data bus is 400 MHz, while its true clock rate (IO buffer frequency) is 200 MHz. Internal clock rate of DDR memory chips (the first generation) equals the true clock rate of the external bus (IO buffer frequency) - 200 MHz for the DDR-400 memory chip. In order to transfer 1 bit per clock (via each data line) along the external bus operating at the effective clock rate of 400 MHz, 2 bits must be transferred per clock of the internal 200 MHz data bus. In other words, we can say that all other things being equal, the internal data bus must be twice as wide as the external data bus. This data access scheme is called 2n-prefetch.

Picture 2. Schematic diagram of data transfer in a DDR2-800 chip.

The most natural solution to this problem of obtaining higher clock rates in DDR2 was to reduce the clock rate of the internal data bus to a half relative to the real clock rate of the external data bus (IO buffer frequency). For example, in case of DDR2-800 memory chips (Picture 2), IO buffer frequency is 400 MHz, and the efficient clock rate of the external data bus is 800 MHz (because Double Data Rate is still in force - data are still transferred both on the rising and falling edge of the clock). Clock rate of the internal data bus is just 200 MHz, so in order to transfer 1 bit (via each data line) per clock of the external data bus operating at the efficient clock rate of 800 MHz, 4 bits must be transferred per clock of the internal 200 MHz data bus. In other words, an internal data bus of DDR2 must be four times as wide as its external bus. This data access scheme, implemented in DDR2, is called 4n-prefetch. It has evident advantages over 2n-prefetch in DDR. On one hand, one can use twice as low internal clock rate of memory chips (200 MHz for DDR-400 and just 100 MHz for DDR2-400, which significantly reduces power consumption) to obtain equal peak memory bandwidth. On the other hand, the internal clock rate of DDR and DDR2 memory chips being equal (200 MHz for DDR-400 and DDR2-800), the latter will have twice as high theoretical bandwidth. But its drawbacks are evident as well - DDR2 chips operate at a twice as low clock rate (with the theoretical bandwidth of DDR and DDR2 being equal) and use a more complex 4-1 conversion, which results in noticeably higher latencies. We saw it in practice, when we tested the first samples of DDR2 memory.

4n-prefetch is not the only innovation in DDR2, of course. But it's the most significant difference from the previous generation of memory (DDR), so it's sufficient for our brief review. You may read more details about DDR2 in our article "DDR2 - the forthcoming replacement of DDR. Theoretical basics and the first low-level test results".

Further development of the DDR2 technology was similar to the development of its previous generation, DDR memory. Namely, the clock rates reached 333 and 400 MHz (that is DDR2-667 and DDR2-800 official standards). Latencies dropped significantly, there appeared a new official version of JEDEC (JESD79-2B), which allows to reduce timings from 4-4-4 to 3-3-3 for DDR2-533, from 5-5-5 to 4-4-4 for DDR2-667, from 6-6-6 to 5-5-5 or even 4-4-4 for DDR2-800. They were followed by non-standard modifications of DDR2, of course. Their clock rate exceeded the JEDEC bounds - up to 625 MHz ("DDR2-1250") with 5-5-5 timings, or "standard" DDR2-800, but with extremely low timings, for example 3-3-3. As before, such results required a significant rise in memory voltage from standard 1.8V to extreme 2.4V (it's a tad lower than the standard voltage for the previous DDR memory generation - 2.5V). It certainly required more advanced ways to channel the heat away from memory chips - original, patented heatsink designs as well as external active cooling.

Nevertheless, as in case with the previous generation of DDR memory, DDR2 technology has almost reached its maximum (in frequency, latencies, and significantly increased heat release owing to much higher voltages). And now we can expect another evolutional leap in the DDR SDRAM technology - DDR3.

Picture 3. Schematic diagram of data transfer in a DDR3-1600 chip.

It's easy to guess that the DDR2-DDR3 upgrade is based on the same principle as the DDR-DDR2 upgrade. Namely, DDR3 is still DDR SDRAM. That is data are still transferred both on the rising and falling edge of the clock at the doubled effective frequency relative to the memory bus clock rate. Only performance ratings have grown twice as high versus DDR2 - typical performance categories of new DDR3 memory will vary from DDR3-800 to DDR3-1600 (and probably higher). The next doubling of theoretical memory bandwidth has again to do with halving of their internal clock rate. That's why in order to reach the data transfer rate of 1 bit per clock along each line of the external data bus operating at the effective frequency of 1600 MHz (as in Picture 3), 200 MHz chips must transfer 8 bits per clock. That is the internal data bus of memory chips will be eight times as wide as their external data bus. This data transfer scheme with "8-1" conversion will evidently be called 8n-prefetch. Advantages of the DDR2-DDR3 upgrade will be the same as in case of the previous DDR-DDR2 upgrade: on one hand, it's a reduction of memory power consumption while preserving peak memory bandwidth (DDR3-800 versus DDR2-800); on the other hand, it's an opportunity to increase memory clock rates and theoretical bandwidth and retain the old level of the internal clock rate (DDR3-1600 versus DDR2-800). Drawbacks will also be the same - a wider gap between the internal and external clock rates of memory buses will result in higher latencies. It's logical to assume that the relative increase in latencies during the DDR2-DDR3 upgrade will be similar to that of the DDR-DDR2 upgrade.

Well, let's proceed to a detailed review of the new generation of memory - DDR3, which will replace DDR2 memory.